Abandoning 4F², HBM4 mass production, G11 NAND acceleration... Micron (MU.US) technical seminar revealed the roadmap, and Komo maintained an “gain” rating

The Zhitong Finance App learned that according to J.P. Morgan's latest research report, Micron Technology (MU.US) detailed its latest technological innovations and long-term plans in the three core product lines of DRAM, HBM, and NAND at an investor technology webinar held on October 21. The bank's analyst team, led by Harlan Sur, believes that Micron's technology roadmap is clear and forward-looking, and is expected to continue to benefit from the explosion in AI-driven storage demand, thus maintaining its “gain” rating.

Adhere to the 6F² DRAM architecture and promote 3D DRAM in parallel

J.P. Morgan Chase pointed out in the report that in terms of the evolution of DRAM architectures, Micron clearly responded to the industry's dispute over 6F² and 4F² technology routes. Micron said that the next generation of DRAM nodes will continue to use a 6F² architecture instead of a 4F² architecture. The company is confident that it will maintain its leading position in power consumption and performance through strict node miniaturization, process innovation, and product-level optimization.

Micron revealed that its research on 4F² DRAM has been going on for about 20 years, but the final decision was not to adopt it, mainly because the architecture is more complex and more expensive, and the company believes that the benefits brought about by its downsizing are limited.

In its research report, J.P. Morgan detailed the three challenges faced by the 4F² architecture in the manufacturing process: first, the architecture requires more intensive deposition and etching processes, which significantly increases the probability of yield problems; secondly, 4F² has more stringent process tolerance requirements (such as stamping, alignment, etc.), which puts more pressure on manufacturability and yield; finally, the architecture itself can easily trigger a “floating body effect” (Floating Body Effect), causing charges to be trapped in the transistor channel, causing performance degradation and electrical leakage problems.

Additionally, Micron also refuted the view that 4F² is superior to 6F² in terms of density, emphasizing that DRAM's bit density is ultimately determined by Capacitor Pitch (Capacitor Pitch), not the underlying interconnect pitch (Interconnect Pitch).

According to the currently announced roadmap, Micron will continue to use a 6F²-based flat architecture (which is expected to continue until 2030) in future generations of DRAM nodes while developing 3D DRAM technology in parallel.

The HBM roadmap is fully broadened, focusing on customization and vertical stacking

In the high-profile HBM field, Micron said that the HBM4 has now entered large-scale mass production and is progressing smoothly. The next generation HBM4E is also on the roadmap, and the company is delivering samples to key customers this year.

Looking ahead, Micron expects standard HBM and custom HBM to coexist for a long time. By integrating memory IP and logic IP into the base die (base die), custom HBM enables deeper customer collaborative design. The Micron team pointed out that future standard JEDEC HBM and custom HBM products will use foundry nodes. Among them, HBM4E will require more advanced CMOS technology due to higher requirements for speed, power consumption and functionality.

In addition to standard and custom HBM, Micron also highlights two important long-term memory architectures: vertical HBM (vertical HBM) and vertical edge inference memory (veIM). Vertical HBM shortens the path between storage and computing by placing the memory directly above the processor, thereby providing a significant increase in bandwidth; vEIM uses a similar approach, but is optimized specifically for low-power edge AI inference use cases (that is, vertical HBM focuses on high bandwidth, and VeIM focuses on low power consumption).

Micron emphasized the growing importance of hybrid bonding, higher stack count, advanced thermal management, and customer collaborative design in the HBM roadmap. However, as HBM, vertical HBM, and Veim advance, these products require more wafers than standard DRAM output, which also means that the wafer-bit output conversion ratio will continue to be under pressure.

NAND upgraded to G11 across generations, AI products expand market space

In the NAND field, after experiencing three consecutive leading nodes from G7 to G9, Micron will go directly to the G11 node optimized for AI workloads. Compared to G9, G11 aims to achieve about 2 times the bit density, up to 1.5 times faster I/O speed, and reduce data transmission energy consumption per bit by more than 25%, and the number of stacking layers will exceed 400.

The G11 node also marks Micron's official introduction of wafer-on-wafer (Wafer-on-wafer) bonding technology in NAND manufacturing. The company expects G11 to be launched in the second half of 2027, and plans to release more details next year. In addition, Micron also plans to continue downsizing after G11 through new materials and higher density unit architectures.

At the product level, Micron is building two AI-grade NAND products: one is based on a high-speed SLC design (providing 25 million to 100 million IOPS), specially designed for GPUs to extract large amounts of small data blocks in tasks such as vector search and AI context retrieval; the second is to stack NAND chips on logic chips through TSV to place model weights, long contexts, and KV caches closer to the accelerator (not directly next to the GPU, because Micron sees no benefit). Due to the high cost, Micron is developing a second product together with the customer. It is expected that the market share of the two products will vary depending on the terminal market.

In terms of data center SSDs, Micron is the first manufacturer to mass-produce PCIe Gen6 SSDs and ship 245TB hard drives. The lower single-bit cost brought by its advanced nodes is expected to support the further growth of high-capacity hard drives. J.P. Morgan believes that Micron's NAND roadmap enables it to fully benefit from the growth in AI-driven storage demand and is expected to maintain or expand its market share in the top three global enterprise SSD (eSSD) markets.

Deepen customer collaboration and long-term R&D, and greatly improve efficiency with AI tools

Micron detailed a major shift in its customer partnership model. Compared to three to four years ago, the current collaboration begins at the conceptual stage and extends from joint design, certification to mass production, including custom projects with multiple cloud service providers (CSPs). For example, Micron is customizing LPDDR6 for Meta (META.US) for data center deployments; while Weka is evolving from a Micron Ventures portfolio company to a commercial partner.

In terms of R&D, Micron's long-term investment has spanned three time dimensions: first, a commitment to invest $550 million in Micron Ventures within 3 to 10 years; second, to cooperate with Albany Nanotech/NY CREATES to develop a DRAM-oriented high numerical aperture (high-NA) EUV and lithography roadmap within 5 to 10 years; and third, the $10 billion Micron research laboratory announced this summer, focusing on a 10-year cycle.

Furthermore, Micron is fully deploying AI technology throughout the entire development cycle from early research to the fab. According to the data, on its latest data center SSD controller, AI-assisted chip design and verification cut the streaming time by half compared to the previous generation; AI-generated firmware, root cause analysis, and intelligent test choices shortened the path for data center SSDs to achieve customer-ready silicon chips by 60%.

Micron aims to double the path from innovation to large-scale mass production (HVM), and is deepening partnerships with suppliers in fields such as lithography, packaging/hybrid bonding, and film processing. J.P. Morgan believes these efforts are critical to Micron's ability to advance more projects in parallel.