Alchip teams with Synopsys on 224G PHY-based design for AI data center ASIC bandwidth constraints

PUBT · 1d ago
Alchip teams with Synopsys on 224G PHY-based design for AI data center ASIC bandwidth constraints
  • Alchip teamed with Synopsys to develop a protocol-agnostic physical design approach for AI data center ASICs using 224G PHY IP.
  • Work targets scale-up and out bandwidth bottlenecks, focusing on die-edge utilization, escape routing, package breakout, signal integrity, power integrity.
  • Design supports up to 1.6 Tbps networking bandwidth, with a path to 448G SerDes implementations.
  • Engineers reported chip-to-chip interconnect bandwidth density near theoretical physical limits within practical die-edge and packaging constraints.


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