“The memory wall is still there, and the situation may even be getting worse.” Raghu Sriramaneni, an expert on the design architecture direction of Micron HBM, expressed this opinion at Hot Chips 2026, a semiconductor academic conference held at Stanford University in the US on the 23rd local time. A memory wall indicates that the performance of the chip responsible for computing is rapidly improving, but the memory responsible for transmitting data cannot keep up with the computational speed, resulting in a performance bottleneck. Since entering the age of artificial intelligence, this bottleneck has not only not been alleviated, but has become more serious. Sri Ramaneni said that the computational performance of AI accelerators increases by about 3 times every 2 years, but the performance of HBM, which is responsible for data supply, has increased less than 2 times over the same period. Even with the most powerful chips, if the data transmission channel is narrow, the final performance will be limited by the channel speed. He predicted, “Breaking the boundary between computing units and memory, and designing a new architecture will be a path to overcome the memory wall.”

“The memory wall is still there, and the situation may even be getting worse.” Raghu Sriramaneni, an expert on the design architecture direction of Micron HBM, expressed this opinion at Hot Chips 2026, a semiconductor academic conference held at Stanford University in the US on the 23rd local time. A memory wall indicates that the performance of the chip responsible for computing is rapidly improving, but the memory responsible for transmitting data cannot keep up with the computational speed, resulting in a performance bottleneck. Since entering the age of artificial intelligence, this bottleneck has not only not been alleviated, but has become more serious. Sri Ramaneni said that the computational performance of AI accelerators increases by about 3 times every 2 years, but the performance of HBM, which is responsible for data supply, has increased less than 2 times over the same period. Even with the most powerful chips, if the data transmission channel is narrow, the final performance will be limited by the channel speed. He predicted, “Breaking the boundary between computing units and memory, and designing a new architecture will be a path to overcome the memory wall.”