MARKET

NLST

NLST

Netlist
OTCMQB
1.380
0.000
0.00%
Opening 12:56 07/26 EDT
OPEN
1.390
PREV CLOSE
1.380
HIGH
1.420
LOW
1.370
VOLUME
73.19K
TURNOVER
101.25K
52 WEEK HIGH
10.20
52 WEEK LOW
0.870
MARKET CAP
355.69M
P/E (TTM)
-5.5803
1D
5D
1M
3M
1Y
5Y
1D
NETLIST INC FILES FOR MIXED SHELF OFFERING OF UP TO $200 MLN - SEC FILING
Reuters · 2d ago
Netlist secures order finalizing $303M damages award against Samsung
Seeking Alpha · 2d ago
Weekly Report: what happened at NLST last week (0715-0719)?
Weekly Report · 4d ago
Weekly Report: what happened at NLST last week (0708-0712)?
Weekly Report · 07/15 11:32
Weekly Report: what happened at NLST last week (0701-0705)?
Weekly Report · 07/08 11:34
Weekly Report: what happened at NLST last week (0624-0628)?
Weekly Report · 07/01 11:35
Weekly Report: what happened at NLST last week (0617-0621)?
Weekly Report · 06/24 11:43
Lawyers on track for mid-year bonuses at US trial firm McKool Smith
Lawyers on track for mid-year bonuses at US trial firm McKool Smith. Dallas-based law firm known for taking on high-stakes patent cases and other litigation. Bonuses for lawyers will range from $2,500 to $30,000 depending on their pace of billing.
Reuters · 06/21 20:23
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About NLST
Netlist, Inc. provides memory solutions to enterprise customers in diverse industries. The Company’s products, in various capacities and form factors, including its line of custom and specialty memory products, bring performance to customers in a variety of industries globally. It also licenses its intellectual property. The Company’s commercially available memory subsystem products and other products that it sells include Component and Other Product Resales and Specialty DIMMs and Embedded Flash. Its portfolio of technologies and design techniques includes Distributed Buffer Architecture; Localized Module-Based Power Management Architecture; Proprietary PCB Designs; Thermal Management Designs; Compute Express Link Technology, and others. Its distributed buffer architecture enables the buffering of data signals using multiple data buffer devices distributed between a memory module’s edge connector and its installed dynamic random-access memory (DRAM).

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